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1 PCM1740 stereo audio digital-to-analog converter with vcxo and pll PCM1740 features l complete delta-sigma stereo dac l voltage-controlled crystal oscillator: 27mhz 150ppm output with 0v to 3v input l programmable pll 256f s or 384f s audio system clock output l dynamic performance: dynamic range: 94db snr: 94db thd+n: C89db l sampling frequencies: 16khz, 22.05khz, 24khz 32khz, 44.1khz, 48khz 64khz, 88.2khz, 96khz l serial audio interface: standard or i 2 s data formats 16-, 20-, or 24-bit data l i 2 c-bus ? interface for control registers (1) : slave receiver operation 7-bit addressing standard transfer rate (up to 100kbps) l programmable controls: digital attenuation (256 steps) soft mute infinite zero detect mute de-emphasis (32khz, 44.1khz, 48khz) dac output mode l single +5v supply l small ssop-24 package ? 2000 burr-brown corporation pds-1551a printed in u.s.a. february, 2000 for most current data sheet and other product information, visit www.burr-brown.com tm description the PCM1740 is a complete stereo audio digital-to-analog converter with on-chip pll and vcxo. the PCM1740 is designed specifically for set-top box applications requiring high-quality audio playback, a precision tuned 27mhz mas- ter clock source, and support for multiple audio-sampling frequencies. the stereo d/a converter utilizes multi-bit, delta-sigma architecture, which includes an 8x interpolation filter, third- order noise shaping, 5-level amplitude quantization, and an analog low-pass filter. the PCM1740 includes a number of user-programmable functions, which are accessed via a standard i 2 c-bus interface. applications l set-top boxes l digital broadcast receivers international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson blvd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate p roduct info: (800) 548-6132 note: (1) i 2 c-bus ? is a registered trademark of philips semiconductor. PCM1740 pcm audio i/f i 2 c i/f and regs vcxo scl sda ad1 ad0 xtun xt1 xt2 rst 27mhz crystal 8x oversampling digital filter and sub-functions process dac (r) counter n v out l v com zero scko (256f s / 384f s ) mcko (27mhz) v out r counter m power supply reset bck lrck data phase detector v pp agnd dgnd v cc v dd pgnd dac (l) low-pass filter and amp lpf vco
2 PCM1740 specifications all specifications at t a = +25 c, v cc = v dd = v pp = 5.0v, f s = 44.1khz, system clock = 384f s , 16-bit data, unless otherwise noted. PCM1740e parameter conditions min typ max units resolution 16 bits data format audio interface format standard/i 2 s selectable audio data bit length 16/20/24 selectable bits audio data format msb first, twos binary complement sampling frequency (f s ) standard (f s ) 32 44.1 48 khz half (f s ) 16 22.05 24 khz double (f s ) 64 88.2 96 khz internal system clock frequency 256f s /384f s digital input/output logic family input logic ttl compatible high level input voltage: v ih (1), (2) 2.0 vdc low level input voltage: v il (1), (2) 0.8 vdc high level input current: i ih (1), (2) v ih = v dd 10 m a low level input current: i il (1) v il = 0v 10 m a i il (2) v il = 0v C120 m a high level output voltage: v oh (3) i oh = C2ma v dd C 0.5v vdc low level output voltage: v oh (3) i ol = 4ma 0.5 vdc v ol (4) i ol = 2ma 0.5 vdc digital input/output of i 2 c-bus interface high level input voltage: v ih (5) 3.0 v low level input voltage: v il (5) C0.3 1.5 v low level output voltage: v ol (6) 0 0.4 v output fall time: t of (7) 250 ns input logic current: i i (8) 10% to 90% of v dd C10 10 m a capacitance for each i/o pin: c i (5) 10 pf vcxo characteristics (mcko) 27mhz, fundamental crystal crystal clock frequency (9) 27.0000 mhz crystal clock accuracy (9) 30 ppm xtun tuning voltage range (10) 0 3.0 v xtun input impedance (10) 60 k w output clock frequency xtun = 1.3v 27.0000 mhz output clock accuracy xtun = 1.3v 50 ppm vcxo tuning range xtun = 0v C 3v 300 ppm output clock duty cycle 10pf load 35 45 55 % output clock jitter standard deviation 100 ps output rise time 20% to 80% v dd , 10pf load 4 ns output fall time 80% to 20% v dd , 10pf load 4 ns response time (11) 10 m s power up time (12) 5ms pll ac characteristics (scko) output clock frequency mcko = 27.0mhz 4.096 36.864 mhz output clock duty cycle 10pf load 40 50 60 % output clock jitter standard deviation 150 ps output rise time 20% to 80% v dd , 10pf load 4 ns output fall time 80% to 20% v dd , 10pf load 4 ns frequency transition time (13) 20 ms power up time (14) 15 30 ms dynamic performance (15) thd+n: v out = 0db f s = 44.1khz 0.0035 0.01 % f s = 96khz 0.007 % v out = C60db f s = 44.1khz 0.0035 0.01 % f s = 96khz 0.007 % dynamic range f s = 44.1khz, eiaj, a-weighted 90 94 db f s = 96khz, a-weighted 90 db signal-to-noise ratio (16) f s = 44.1khz, eiaj, a-weighted 90 94 db f s = 96khz, a-weighted 90 db channel separation f s = 44.1khz 88 92 db f s = 96khz 88 db level linearity error v out = C90db 1.0 db
3 PCM1740 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. dc accuracy gain error 1.0 3.0 % of fsr gain mismatch, channel-to-channel 1.0 3.0 % of fsr bipolar zero error 1.0 % of fsr analog output voltage range full scale (0db) 0.62 v cc vp-p center voltage 0.5 v cc vdc load impedance ac coupled 5 k w digital filter performance passband 0.445 f s hz stopband 0.555 f s hz passband ripple 0.17 db stopband attenuation C35 db de-emphasis error C0.2 +0.55 db delay time 11.125 / f s sec analog filter performance frequency response 20hz to 20khz C0.16 db 20hz to 40khz C0.6 db power supply requirements voltage range v dd , v cc , v pp +4.5 +5 +5.5 vdc supply current, i dd + i cc + i pp v dd = v cc = v pp = +5v 25 30 ma power dissipation v dd = v cc = v pp = +5v 125 150 mw temperature range operation C25 +85 c storage C55 +125 c thermal resistance, q ja 100 c/w notes: (1) pins 6, 7, 18, 19: ad0, ad1, bck, data, lrck (schmitt trigger input). (2) pin 10: rst (schmitt trigger input with in ternal pull-up resistor). (3) pins 5, 21: mcko, scko. (4) pin 16: zero (open drain output). (5) pins 8, 9: scl, sda. (6) pin 9: sda (open drain output, i ol = 3ma). (7) pin 9: sda (from v ihmin to v ilmax with a bus capacitance from 10pf to 400pf). (8) pins 8, 9: scl, sda (input current each i/o pin with an input voltage between 0.1v dd and 0.9v dd ). (9) this characteristic is the requirement for crystal oscillator. (10) pin 3: xtun. (11) the maximum response time when the xt un is changed. (12) the maximum delay time from power on to oscillation. (13) the maximum lock up time when the pll frequency is changed. (14) the maximum dela y time from power on to lock up. (15) dynamic performance specifications are tested with a 20khz low-pass filter using a shibasoku distortion analyzer 725 c with 30khz lpf, 400hz hpf, average-mode. (16) snr is tested with infinite zero detection circuit disabled. PCM1740e parameter conditions min typ max units specifications all specifications at t a = +25 c, v cc = v dd = v pp = 5.0v, f s = 44.1khz, system clock = 384f s , 16-bit data, unless otherwise noted.
4 PCM1740 pin name i/o function 1 xt1 27mhz crystal connection. 2 pgnd pll and vcxo ground. 3 xtun in vcxo tune, tuning voltage range from 0v to 3v. 4v pp pll and vcxo power supply, +5v. 5 mcko out buffered clock output of vcxo. 6 ad0 in device address pin for i 2 c-bus. (1) 7 ad1 in device address pin for i 2 c-bus. (1) 8 scl in bit clock input for i 2 c-bus interface. 9 sda in/out serial data for i 2 c-bus interface. 10 rst in reset, active low. (2) 11 v out r out right-channel analog voltage output. 12 agnd analog ground. 13 v cc analog power supply, +5v. 14 v out l out left-channel analog voltage output. 15 v com dc common-mode voltage output. 16 zero out zero flag output, active low. (3) 17 bck in bit clock input for serial audio data. (1) 18 data in serial audio data input. (1) 19 lrck in left and right word clock, equal to the sampling rate (f s ). (1) 20 rsv reserved must be open. 21 scko out system clock output, 256/384 f s . 22 v dd digital power supply, +5v. 23 dgnd digital ground. 24 xt2 27mhz crystal connection. notes: (1) schmitt trigger input. (2) schmitt trigger input with internal pull-up resistor. (3) open drain output. power supply voltage (1) ................................................................... +6.5v supply voltage differences (2) ........................................................... 0.1v gnd voltage differences (3) .............................................................. 0.1v digital input voltage ................................................. C0.3v to (v dd + 0.3v) analog input voltage ................................................ C0.3v to (v cc + 0.3v) input current (any pins except supplies) ........................................ 10ma operating temperature range ......................................... C25 c to +85 c storage temperature ...................................................... C55 c to +125 c junction temperature .................................................................... +150 c lead temperature (soldering, 5s) .................................................. +260 c package temperature (ir reflow, peak, 10s) ................................ +235 c notes: (1) v cc , v dd , v pp . (2) among v cc , v dd , v pp . (3) among agnd, dgnd, and pgnd. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. pin assignments pin configuration top view ssop absolute maximum ratings electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package specified drawing temperature package ordering transport product package number range marking number (1) media PCM1740e ssop-24 338 C25 c to +85 c PCM1740e PCM1740e rails " " " " PCM1740e PCM1740e/2k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k indicates 2000 dev ices per reel). ordering 2000 pieces of PCM1740e/2k will get a single 2000-piece tape and reel. package/ordering information xt1 pgnd xtun v pp mcko ad0 ad1 scl sda rst v out r agnd PCM1740 xt2 dgnd v dd scko rsv lrck data bck zero v com v out l v cc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
5 PCM1740 typical performance curves at t a = +25 c, v cc = v dd = +5v, f s = 44.1khz, f scko = 384f s = 16.9344mhz, and 16-bit data, unless otherwise noted. frequency response (de-emphasis off, f s = 44.1khz) f s level (db) 0 ?0 ?0 ?0 ?0 ?00 01234 passband ripple (de-emphasis off, f s = 44.1khz) f s level (db) 0 ?.2 ?.4 ?.6 ?.8 ? 0 0.2 0.1 0.3 0.4 0.5 de-emphasis frequency response (3khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 de-emphasis frequency response (44.1khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 de-emphasis frequency response (48khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 level (db) level (db) level (db) de-emphasis error (3khz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 frequency (hz) 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 de-emphasis error (44.1khz) frequency (hz) de-emphasis error (48khz) frequency (hz) error (db) error (db) error (db)
6 PCM1740 typical performance curves (cont.) at t a = +25 c, v cc = v dd = +5v, f s = 44.1khz, f scko = 384f s = 16.9344mhz, and 16-bit data, unless otherwise noted. analog filter (1hz to 10mhz) log frequency (hz) level (db) 20 0 ?0 ?0 ?0 ?0 ?00 0 0.2 0.1 0.1 0.3 0.4 0.4 0.5 analog filter (1hz to 20khz) log frequency (hz) level (db) 0.05 0 ?.05 ?.1 ?.15 110 1k 100 10k 100k supply current vs sampling frequency sampling frequency (khz) supply current (ma) 35 30 25 20 32 64 88.2 44.1 48 96.0 thd+n (fs), dynamic range, and snr vs supply voltage (temperature = 25 c, 384f s , f s = 44.1khz) supply voltage (v) thd+d (fs) (%) 0.005 0.004 0.003 0.002 0.001 0.000 dynamic range, snr (db) 95 94 93 92 91 90 4.25 4.5 5.25 4.75 5 5.5 5.75 snr thd+n dynamic range thd+n (fs), dynamic range, and snr vs temperature (v cc = v dd = v pp = 5v, 384f s , f s = 44.1khz) temperature ( c) thd+d (fs) (%) 0.005 0.004 0.003 0.002 0.001 0.000 dynamic range, snr (db) 95 94 93 92 91 90 ?0 ?5 50 0 25 75 100 snr thd+n dynamic range thd+n (fs), dynamic range, and snr vs sampling frequency sampling frequency (khz) thd+d (fs) (%) 0.010 0.008 0.006 0.004 0.002 0.000 dynamic range, snr (db) 96 94 92 90 88 86 32 64 88.2 44.1 48 96.0 snr thd+n dynamic range
7 PCM1740 3rd order ds modulator frequency (khz) gain (?b) 20 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 0 5 10 15 20 25 stereo digital-to-analog converter the stereo d/a converters of the PCM1740 utilize a multi- level delta-sigma architecture. based upon a third-order noise shaper and a 5-level amplitude quantizer, this section converts the 8x oversampled, 18-bit input data from the interpolation filter to a 5-level delta-sigma format. a block diagram of the multi-level delta-sigma modulator is shown in figure 1. this architecture has the advantage of improved stability and increased tolerance to clock jitter when com- pared to the one-bit (2-level) delta-sigma d/a converters. the combined oversampling rate of the delta-sigma modu- lator and the 8x interpolation filter is 48f s for a 384f s system clock, and 64f s for a 256f s system clock. the theoretical quantization noise performance for the 5-level delta-sigma modulator is shown in figure 2. the output of the delta-sigma modulator is low-pass filtered and buffered by an on-chip output amplifier. for best performance, an external low-pass filter is recommended. refer to the applications information section of this data sheet for details regarding dac output filter recommenda- tions. the PCM1740 includes two analog outputs, v out l (pin 14) and v out r (pin 11), corresponding to the left and right audio outputs. the full-scale output amplitude is 0.62 ? v cc , or 3.1vp-p with a +5v supply and an ac coupled load of 5k w or greater. the analog outputs are centered about the dc common mode voltage, which is typically v cc /2. the dc common-mode voltage is made available at the v com output (pin 15). this is an unbuffered output, prima- out 48f s (384f s ) 64f s (256f s ) in 8f s 18-bit + + + 4 3 2 1 0 5-level quantizer + + z ? + + z ? + + z ? figure 2. quantization noise spectrum. rily used for de-coupling purposes. see the applications information section of this data sheet for more information regarding the use of the v com output for biasing external circuitry. voltage controlled crystal oscillator (vcxo) the PCM1740 includes an on-chip voltage-controlled crys- tal oscillator, or vcxo, which is used to generate the 27mhz master clock required by most digital broadcast and mpeg-2 decoding applications. figure 1. 5-level ds modulator block diagram.
8 PCM1740 the 27mhz clock is available at the mcko output (pin 5). the vcxo output frequency can be precisely tuned using a control voltage at the xtun input (pin 3). the tuning range is 27mhz 150ppm typical for a 0v to +3v control voltage range. figure 3 shows the vcxo equivalent circuit, while figure 4 shows the typical tuning curve. at power up, the vcxo requires 5ms start up time. the vcxo also exhibits a 10 m s settling time in response to changes in the xtun control voltage. vcxo operation and the mcko output are not effected by the power on or external reset functions, continuing to operate during the initialization sequence. crystal selection the vcxo connects to an external 27mhz crystal via xt1 (pin 1) and xt2 (pin 24). the crystal should be at-cut, fundamental mode with 30ppm accuracy and less than 50 w motional resistance. crystal shunt capacitance should be 3pf maximum, while load capacitance should be less than 7pf. miniature lead type or surface-mount devices are recom- mended. external load capacitors are not needed, since they are provided on-chip. the crystal should be placed as close as possible to the xt1 and xt2 pins to reduce effects of parasitic capacitance and land resistance. programmable phase locked loop (pll) the PCM1740 includes an on-chip pll for generating a 256f s or 384f s audio system clock from the 27mhz vcxo output. a block diagram of the pll section is shown in figure 5. the pll output clock is used by the digital filter and delta-sigma modulator circuitry, and is made available at the scko output (pin 21) for use with additional audio converters and signal processors. tuning voltage (v) vcxo output frequency (mhz) 27.005 27.004 27.003 27.002 27.001 27.000 26.999 26.998 26.997 26.996 26.995 0.0 0.5 1.5 1.0 2.0 2.5 3.0 3.5 4.0 27mhz crystal xtun 0v to +3v vcxo mcko 27mhz 150ppm scko 256/384f s frequency selection rom phase detector and loop filter pll n counter frequency selection control register 3 vco m counter figure 3. vcxo equivalent circuit. figure 4. vcxo output frequency (mcko) versus tuning voltage (xtun). xt1 27mhz crystal 27mhz tuned clock voltage range 0 to 3v 1 24 3 xtun c lv xt2 c l figure 5. pll block diagram.
9 PCM1740 the pll can generate one of nine pre-programmed system clock rates for either 256f s or 384f s output. the pll output and sampling frequencies are programmed using control register 3. table i shows the available sampling frequencies and the corresponding pll output clock rates. the reset default condition for the pll is f s = 44.1khz with scko = 384f s , or 16.9344mhz. at power up, the pll requires 30ms start up time for stabilization. the pll also exhibits a settling time of 20ms in response to changes in sampling frequency selection. the pll output continues to operate during power on or external reset sequences, with the sampling frequency set to f s = 44.1khz and scko = 384f s . reset operation power on reset the PCM1740 includes power-on reset circuitry for start up initialization. the initialization sequence starts when v dd exceeds 2.2v (typical). the initialization sequence requires 1024 pll output (or scko) clock cycles for completion. during initialization, both v out l and v out r are forced to v cc / 2. figure 6 shows the power on reset timing, while table ii shows the reset default settings for user-program- mable functions. the user should not attempt to write control registers via the i 2 c-bus interface during the initial- ization sequence. external reset the PCM1740 includes an external reset input, rst (pin 10). this input may be used to force an initialization se- quence. as shown in figure 7, the rst pin must be held low for a minimum of 20ns. the initialization sequence will then start on the rising edge of rst. initialization requires 1024 pll output (or scko) clock cycles for completion. during initialization, both v out l and v out r are forced to v cc /2. table ii shows the reset default settings for user-program- mable functions. the user should not attempt to write control registers via the i 2 c-bus interface during the initial- ization sequence. sampling internal system internal system frequency (lrck) clock - 256f s clock - 384f s 16khz half 4.096mhz 6.144mhz 32khz normal 8.192mhz 12.288mhz 64khz double 16.384mhz 24.576mhz 22.05khz half 5.6448mhz 8.4672mhz 44.1khz normal 11.2896mhz 16.9344mhz 88.2khz double 22.5792mhz 33.8688mhz 24khz half 6.144mhz 9.216mhz 48khz normal 12.288mhz 18.432mhz 96khz double 24.576mhz 36.864mhz table i. pll sampling and system clock frequencies. 1024 system clock periods reset reset removal 2.4v 2.2v 2.0v v cc /v dd internal reset system clock (scko) 1024 system clock periods reset reset removal system clock (scko) internal reset rst t rst t rst t rst 3 20ns figure 6. power-on reset operation. figure 7. external reset operation.
10 PCM1740 lrck bck data scko frame sync serial bit clock serial data output audio clock PCM1740 audio dsp/decoder 14 15 16 1 2 3 14 15 1/fs l_ch r_ch msb lsb 16 lrcin (pin 4) (a) standard right - justified format (b) i 2 s format bckin (pin 6) audio data word = 16-bit din (pin 5) 1 2 3 14 15 msb lsb 16 18 19 20 1 2 3 18 19 msb lsb 20 audio data word = 20-bit din (pin 5) 1 2 3 18 19 msb lsb 20 23 24 1 2 3 22 23 msb lsb 24 audio data word = 24-bit din (pin 5) 1 2 3 22 23 msb lsb 24 1 2 3 14 15 1/fs l_ch r_ch msb lsb 16 lrcin (pin 4) bckin (pin 6) audio data word = 16-bit din (pin 5) 1 2 3 14 15 msb lsb 16 1 2 3 18 19 msb lsb 20 audio data word = 20-bit din (pin 5) 1 2 3 18 19 msb lsb 20 2 1 2 1 2 1 1 2 3 22 23 msb lsb 24 audio data word = 24-bit din (pin 5) 1 2 3 22 23 msb lsb 24 the lrck input is operated at the sampling frequency, f s . the bck input is operated at 32, 48, or 64 times the sampling frequency. both lrck and bck must be syn- chronous with the scko output for proper operation. data formats the PCM1740 supports two audio interface formats: stan- dard and i 2 s. these formats are shown in figure 9. the audio data word length for the left and right channels may be 16-, 20-, or 24-bits. the audio data word length and format are programmed using control registers 2 and 3. the reset default condition is standard format with 16-bit audio data. timing requirements figure 10 shows the audio interface timing requirements. zero flag output the PCM1740 includes a zero flag output, zero (pin 16). this is an open-drain output, and a 10k w pull-up resistor connected to v dd is recommended when using the zero flag as a logic output. the PCM1740 includes an infinite zero detection function that monitors the audio data at the data input (pin 18). if the audio data for both the left and right channels is all zeros for 65,536 continuous bck clock cycles, the zero flag will be activated, turning on a mosfet switch and connecting the zero pin to ground. this provides an active low output that may be used to control an external mute circuit, or as a logic indicator for an audio dsp/decoder or microprocessor. audio serial interface the PCM1740 includes a three-wire serial audio interface. this includes lrck (pin 19), bck (pin 17), and data (pin 18). the lrck input is the audio left/right clock, which is used as a latch signal for the interface. the bck input is used to clock audio data into the serial port. the data input carries multiplexed data for the left and right audio channels. audio data must be twos complement, msb first formatted. figure 8 shows the typical connection be- tween the PCM1740 audio serial interface and an audio dsp or decoder. lrck and bck rates figure 8. interfacing the PCM1740 to an audio dsp. figure 9. audio interface formats.
11 PCM1740 loss of synchronization ideally, lrck and bck will be derived from the scko output, ensuring synchronous operation. for other cases, the PCM1740 includes circuitry to detect loss of synchroniza- tion between the lrck and the system clock, scko. a loss of synchronization condition is detected when the phase relationship between scko and lrck exceeds 6 bck cycles during one sample period, or 1/f s . if a loss of synchronization condition is detected, the dac operation will halt within one sample period and the analog outputs will be forced to v cc / 2 until re-synchronization between lrck and scko is completed. figure 11 shows the state of the analog outputs given a loss of synchronization event. during the undefined states, as well as transitions between normal and undefined states, the analog outputs may gener- ate audible noise. user programmable functions the PCM1740 includes a number of programmable func- tions, which are configured using five control registers. these registers are accessed using the i 2 c-bus interface. this section describes the control registers, while the i 2 c-bus interface is described in a later section. table ii lists the available functions and their corresponding reset default condition. register map the control register map is shown in table iii. sub-address bits b8 through b10 are used to specify the register that is being written. all reserved bits, shown as res, must be set to 0. register descriptions the following pages provide detailed descriptions of the five control registers and their associated functions. all reserved bits, shown as res, must be set to 0. figure 10. audio interface timing. figure 11. loss of synchronization and analog output state. register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 0 res res res res res a2 a1 a0 al7 al6 al5 al4 al3 al2 al1 al0 register 1 res res res res res a2 a1 a0 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 register 2 res res res res res a2 a1 a0 pl3 pl2 pl1 pl0 iw1 iw0 dem mut register 3 res res res res res a2 a1 a0 sf1 sf0 dsr1 dsr0 sys atc lrp iis register 4 res res res res res a2 a1 a0 res res res res res ope izd ld sub address byte data byte table iii. control register map. function mode by default audio data format select: standard format / i 2 s format standard format audio data word select: 16-bit /20-bit / 24-bit 16-bit polarity of lr-clock selection left/right = high/ low de-emphasis control: off, 32khz, 44.1khz, 48khz off soft mute control off attenuation data for left-channel 0db attenuation data for right-channel 0db attenuation data mode control left-channel, right-channel individually analog output mode select stereo mode infinity zero detect mute control off dacs operation control on system clock select: 256f s /384f s 384f s sampling frequency select: 32khz group, 44.1khz group, 48khz group 44.1khz group sampling frequency multiplier: normal/ double/ half normal, x1 table ii. user-programmable functions. normal normal synchronous asynchronous within 1/f s synchronous undefined data undefined data v com (= 0.5 v cc ) 22.2/f s state of synchronization v out lrckin bckin din 1.4v 1.4v 1.4v t bch t bcl t lb t bl t ds bckin pulse cycle time bckin pulse width high bckin pulse width low bckin rising edge to lrcin edge lrcin edge to bckin rising edge din set-up time din hold time : t bcy : t bch : t bcl : t bl : t lb : t ds : t dh : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns (min) : 30ns (min) t dh t bcy
12 PCM1740 register definitions b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 0 res res res res res 0 0 0 al7 al6 al5 al4 al3 al2 al1 al0 left channel attenuation data default: al[7:0] = ff hex register 0 is used to set the digital attenuation level for the left channel. if the atc bit in register 3 is set to 1, then this data is also used to control the right channel attenuation. the attenuation level is defined by the following relationships: attenuation (db) = 20 x log (al[7:0] dec ? 256), when al[7:0] = 01 hex (1 dec ) through fe hex (254 dec ) attenuation (db) = C (or mute), when al[7:0] = 00 hex attenuation (db) = 0db, when al[7:0] = ff hex the attenuation load bit, ld, in register 4 must be set to 1 in order to update attenuation settings. if ld is set to 0, the attenuation remains at the previously programmed level, ignoring the new data until ld is set to 1. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 1 res res res res res 0 0 1 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 right channel attenuation data default: ar[7:0] = ff hex register 1 is used to set the digital attenuation level for the right channel. if the atc bit in register 3 is set to 1, then the left channel attenuation data in register 1 is used to control the right channel attenuation. the attenuation level is defined by the following relationships: attenuation (db) = 20 x log (ar[7:0] dec ? 256), when ar[7:0] = 01 hex (1 dec ) through fe hex (254 dec ) attenuation (db) = C (or mute), when ar[7:0] = 00 hex attenuation (db) = 0db, when ar[7:0] = ff hex the attenuation load bit, ld, in register 4 must be set to 1 in order to update attenuation settings. if ld is set to 0, the attenuation remains at the previously programmed level, ignoring the new data until ld is set to 1. mut soft mute control the mut bit controls the soft mute function. soft mute changes the digital attenuation level for both the left and right channels, stepping from the currently programmed value to infinite attenuation one step per sample period, or 1/f s . this provides a quiet muting of the outputs without audible noise. mut = 0 soft mute disabled (default) mut = 1 soft mute enabled dem digital de-emphasis the dem bit controls the digital de-emphasis function, which is valid only for 32khz, 44.1khz, and 48khz sampling frequencies. the de-emphasis plots are shown in the typical performance curves section of this data sheet. dem = 0 de-emphasis off (default) dem = 1 de-emphasis on b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 2 res res res res res 0 1 0 pl3 pl2 pl1 pl0 iw1 iw0 dem mut
13 PCM1740 iw0 audio data word length iw1 the iw0 and iw1 bits are used to select the data word length for the audio serial interface. the audio data format is selected using the iis bit in register 3. iw1 iw0 word length 0 0 16-bits (default) 0 1 20-bits 1 0 24-bits 1 1 reserved pl[3:0] analog output mode select bits pl[3:0] are used to set the output mode for the analog outputs. refer to the table below. pl3 pl2 pl1 pl0 v out lv out r notes 0 0 0 0 mute mute mute 0 0 0 1 left mute 0 0 1 0 right mute 0 0 1 1 (l+r)/2 mute 0 1 0 0 mute left 0 1 0 1 left left 0 1 1 0 right left reverse 0 1 1 1 (l+r)/2 left 1 0 0 0 mute right 1 0 0 1 left right stereo (default) 1 0 1 0 right right 1 0 1 1 (l+r)/2 right 1 1 0 0 mute (l+r)/2 1 1 0 1 left (l+r)/2 1 1 1 0 right (l+r)/2 1 1 1 1 (l+r)/2 (l+r)/2 mono iis audio data format the iis bit is used to select the audio data format, either standard right justified or i 2 s. iis = 0 standard right justified (default) iis = 1 i 2 s lrp lrck polarity the lrp bit selects the polarity of left/right clock input (lrck) when using the standard right justified audio data format. this bit has no effect when using the i 2 s audio data format. lrp = 0 left channel when lrck = high; right channel when lrck = low (default) lrp = 1 left channel when lrck = low; right channel when lrck = high atc attenuation mode control the atc bit is used to select independent or common attenuation data for the left and right channels. atc = 0 independent: left channel uses register 0 and right channel uses register 1 (default) atc = 1 common: left and right channels both use register 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 3 res res res res res 0 1 1 sf1 sf0 dsr1 dsr0 sys atc lrp iis
14 PCM1740 sys audio system clock (or scko) the sys bit is used to select the system clock (or scko) frequency, either 256f s or 384f s . sys = 0 384f s (default) sys = 1 256f s dsr0 sampling frequency multiplier dsr1 the dsr0 and dsr1 bits are used to select the multiplier used in conjunction with the sf0 and sf1 bits. dsr1 dsr0 multiplier 0 0 normal, x1 (default) 0 1 double, x2 1 0 half, x 1/ 2 1 1 reserved sf0 sampling frequency select sf1 the sf0 and sf1 bits are used to select the sampling frequency group (32khz, 44.1khz, or 48khz). the dsr0 and dsr1 bits, described previously, are used to select the multiplier. sf1 sf0 sampling frequency group 0 0 44.1khz group ( 22.05khz, 44.1khz, or 88.2khz) (default) 0 1 48 khz group (24khz, 48khz, or 96khz) 1 0 32 khz group (16khz, 32khz, or 64khz) 1 1 reserved ld attenuation data load control the ld bit is used to simultaneously set the left and right digital attenuation data. when ld is set to 1, the digital attenuation data given by registers 0 and 1 is loaded for the left and right channels. when ld is set to 0, updates to registers 0 and 1 are ignored, and the attenuation settings remain as previously programmed until ld is set to 1. ld = 0 disabled ld = 1 enabled: left and right attenuation data updated simultaneously izd infinite zero detect mute the izd bit is used to enable/disable the infinite zero detect mute function. the PCM1740 includes infinite zero detection logic that monitors the audio data at the data input (pin 18). if the audio data for both the left and right channels is all zeros for 65,536 continuous bck clock cycles, the zero flag will be activated and output amplifier will be disconnected from the output of the delta-sigma modulator. the output amplifiers input is switched to the dc common mode voltage. this forces v out l and v out r to v cc / 2. the zero output flag (pin 16) is not affected by the setting of this bit. izd = 0 disabled (default) izd = 1 enabled ope dac operation control the ope bit is used to enable/disable the operation of the d/a converters. when enabled, the dac outputs are connected to the output amplifier for normal operation. when disabled, the output amplifier is disconnected from the dac output and switched to the dc common mode voltage. this forces v out l and v out r to v cc /2. ope = 0 enabled: normal operation(default) ope = 1 disabled: outputs forced to v cc /2 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 4 res res res res res 1 0 0 res res res res res ope izd ld
15 PCM1740 i 2 c-bus interface description the PCM1740 includes an i 2 c-bus interface for writing the internal control registers. this provides an industry standard method for interfacing a host cpu control port to the PCM1740. the PCM1740 operates as a slave receiver on the bus, and supports data transfer rates up to 100 kilobits- per-second (kbps). the i 2 c-bus interface is comprised of four signals: sda (pin 9), scl (pin 8), ad0 (pin 6), and ad1 (pin 7). the scl input is the serial data clock, while sda is the serial data input. sda carries start/stop, slave address, sub-address (or register address), register, and acknowledgment data. the ad0 and ad1 inputs form the lower two bits of the slave address. slave address the PCM1740 slave address consists of seven bits, as shown in figure 12. the five most significant bits are fixed, while the two least significant bits, named a0 and a1, are defined by the logic levels present at the ad0 and ad1 input pins. this allows four PCM1740s to reside on the same i 2 c-bus. bus operation figure 13 shows the typical configuration of the PCM1740 on the i 2 c-bus. the master transmitter or transmitter/receiver is typically a microcontroller, or an audio dsp/decoder. the master device controls the data transfers on the bus. the PCM1740 operates as a slave receiver, and accepts data from the master when it is properly addressed. the data transfer may be comprised of an unlimited number of bytes, or 8-bit data words. figure 14 shows the message transfer protocol. for normal bit transfer on the bus, data on sda must be static while scl is high. data on sda may change high / low states when scl is low. the exception to this rule is the start and stop conditions. the start condition is defined by a high-to-low transition on sda while scl is high, and is denoted with an s in figure 12. the stop condition is defined by a low-to-high transition on sda while scl is high, and is denoted with a p in figure 12. the start and stop conditions are always generated by the master. all data transfers from master to slave begin with a start condition and end with a stop condition. the bus is considered to be busy after the start condition, and becomes free some time after the stop condition. master transmitter/ receiver scl sda slave receiver (PCM1740) slave transmitter/ receiver master transmitter/ receiver sda scl start condition start condition stop address address r/w r/w ack ack ack data 1-7 1-7 8 8 9 9 9 8 1-7 notes: (1) clock low (min) = 4.7 s; clock high (min) = 4 s. (2) the dased line is the acknoweledgement of the receiver. (3) mark-to space ratio = 1:1 (low-to-high). (4) maximum number of bytes is unrestriced. (5) premature termination of transfer is allowed by generation of stop condition. (6) acknowledge clock bit must be provided by master. figure 12. control data format. figure 13. typical i 2 c-bus configuration. figure 14. i 2 c bus data transfer. 01 slave address 1a1a0 s1 0 0 msb r/w a b12 b11 b10 b15 b14 b13 b09 b08 a b07 b06 b02 b01 b00 b05 b04 b03 a internal strobe for data latching not acknowledge p acknowledge from slave acknowledge from slave start from master stop from master sub address byte data byte
16 PCM1740 data transfer begins with a start condition, and is immedi- ately followed by the slave address and read / write bit. the read/ write bit is set to 0 for the PCM1740, in order to write data to the control register specified by the sub- address. this is followed by an acknowledgment from the PCM1740, the sub-address (i.e., control register address), another acknowledgment from the PCM1740, the control register data, and another acknowledgment from the PCM1740. what happens after this depends upon if the user wants to continue writing additional control registers, or if they want to terminate the data transfer. if the user wants to continue, the acknowledgment is followed by a start condi- tion for the next write sequence. if the user decides to terminate the data transfer, then a stop condition is gener- ated by the master. the i 2 c-bus specification defines timing requirements for devices connected to the bus. timing requirements for the PCM1740 are shown in figure 15. reference for additional information regarding the i 2 c-bus, please refer to the i 2 c-bus specification, version 2.0, published in december 1998 by philips semiconductors. figure 15. i 2 c bus timing. sda scl s: start condition sr: repeated start condition p: stop condition t f t hd; sta s sr p s t hd; dat t high t su; sta t su; sto t r t hd; sta t r t low t f t su, dat t buf symbol description min typ max units f scl scl clock frequency 100 khz t hd; sta hold time (repeated) start condition, 4.0 m s after this period, the first clock pulse is generated t low low period of the scl clock 4.7 m s t high high period of the scl clock 4.0 m s t su:sta set-up time for a repeated start condition 4.7 m s t hd;dat data hold time for i 2 c-bus devices 0 3.45(2) m s t su;dat data set-up time 250 ns t r rise time of both sda and scl signals 1000 ns t f fall time of both sda and scl signals 300 ns t su;sto set-up time for stop condition 4.0 m s t buf bus free time between a stop and start 4.7 m s condition c b capacitive load for each bus line 400 pf v nl noise margin at the low level for each 0.1 v dd v connected device (including hysteresis) v nh noise margin at the high level for each 0.2 v dd v connected device (including hysteresis)
17 PCM1740 figure 16. basic connection diagram. + + xt1 pgnd xtun v pp mcko ad0 ad1 scl sda rst v out r agnd 1 2 3 4 5 6 7 9 8 10 xt2 dgnd v dd scko rsv lrck data bck zero v com v out l v cc i 2 c bus and reset control from p vcxo control voltage (0v to +3v) 27mhz master clock low pass filter (2) right channel output from audio decoder serial interface 256/384f s to audiodecoder and data converters buffer (1) buffer (1) x c 3 10k w zero flag + c 4 + c 5 c 6 notes: (1) use buffer when driving multiple nodes. (2) see applications information section for filter recommendations. c 1 + PCM1740 27mhz crystal c 1 to c 6 = 1 f to 10 f capacitors ( aluminum electrolytic or tantalum) low pass filter (2) left channel output analog ground c 2 +5v + applications information basic connection diagram a basic connection diagram is shown in figure 16. power supply and reference de-coupling capacitors should be located as close as possible to the PCM1740 package. the 27mhz crystal should also be located as close as possible to the package, to reduce the effects of parasitic capacitance on vcxo operation. a single +5v supply is recommended, to avoid issues with power-supply sequencing and scr latch-up. it is recom- mended that this supply be separate from the systems digital power supply. in cases where this is not practical, an audio serial i/f i 2 c i/f and regs vcxo ad1 ad0 scl sda i2c-bus gpio xtun xti xto rst 27mhz crystal 8x interpolation filter and programmable functions dac (r) counter n v out l v com zero scko mcko to audio decoder and data converters to other devices v out r counter m power supply reset bcin lrcin din v cp agnd dgnd v cc v dd pgnd dac (l) low-pass filter and output amp audio decoder mpeg system controller 27mhz reference generated by receive counter line-out_l line-out_r lpf pd vco low-pass filter and analog mute lpf vcxo control voltage phase detec. figure 17. typical application diagram. inductor or ferrite bead should be placed in series with the +5v supply connection to reduce or eliminate high-fre- quency noise on the supply line. in cases where overshoot or ringing is present on the lrck or bck signals, a series resistance of 25 w to 100 w should be added. the resistor forms a simple rc filter with the device input and pcb parasitic capacitance, dampening the overshoot and ringing effects, while reducing high-frequency noise emissions. typical application diagram figure 17 shows the PCM1740 being used as part of the audio sub-system in a set-top box application.
18 PCM1740 the vtun control voltage is generated by the mpeg-2 controller, which compares the mcko output clock from the PCM1740 with the clock count received from the trans- mitter. vtun is adjusted to retain clock synchronization between the transmitted and received signals. the scko output is used as the audio master clock for the audio decoder and additional data converters. v com output the unbuffered dc common-mode voltage output, v com (pin 15), is brought out mainly for de-coupling purposes. v com is nominally biased to v cc /2. the v com output may be used to bias external circuits, but it must be connected to a high-impedance node or buffered using a voltage follower. figure 18 shows examples of the proper use of the v com output for external biasing applications. dac output filtering delta-sigma d/a converters utilize noise shaping tech- niques to improve in-band signal-to-noise (snr) perfor- mance at the expense of generating increased out of band noise above the nyquist frequency, or f s /2. the out of band noise must be low-pass filtered in order to provide optimal converter performance. this is accomplished by a combina- tion of on-chip and external low-pass filtering. the PCM1740 includes an on-chip low-pass filter as part of the output amplifier stage. the frequency response for the filter is shown in the typical performance curves section of this data sheet. the C3db cutoff frequency is fixed at 100khz. figure 19 shows the recommended external low-pass active filter circuits for dual and single-supply applications. these circuits are second-order butterworth filters using the mul- tiple feedback (mfb) circuit arrangement. both filters have a cutoff frequency of 30khz. figure 19(a) is a dual-supply filter with a gain of 1.85 (for a standard 2 v rms line output level). figure 19(b) is a single-supply filter with a gain of 1. values for the filter components may be calculated using the filterpro program, available from the burr-brown web site (www.burr-brown.com) and local sales offices. for more information regarding mfb active filter design and the filterpro program, please refer to burr-brown applications bulletin, ab-034. since the overall system performance is defined primarily by the quality of the d/a converters and their associated analog output circuitry, op amps designed specifically for audio applications are recommended for the active filters. burr-browns opa2134, opa2353, and opa2343 dual op amps are ideal for use with the PCM1740. figure 18. using v com to bias external circuitry. + v out non-polarized 1 f PCM1740 1-10 f v com v cc PCM1740 opa337 opa343 + 1-10 f use voltage follower to buffer v com to bias nodes v com (a) biasing an external active filter stage (b) using a buffer to provide bias for multiple or low input impedance nodes
19 PCM1740 r 1 3.16k w r 2 5.76k w r 3 10k w c 1 220pf c 2 2200pf 1 f to 10 f + + + 1 f to 10 f (a) dual-supply filter circuit filtered output v out r/l PCM1740 +v a ? a opa134 series r 1 3.83k w r 2 3.83k w r 3 15k w c 1 220pf v cc 2 c 2 2200pf (b) single-supply filter circuit 4.7 f to 10 f filtered output v out r/l v com PCM1740 1 f to 10 f v cc opa343/353 series figure 19. recommended output filter circuits.
20 PCM1740 package drawing

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